(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for managing redundancy in memory arrays.
(2) Description of Prior Art
Computer memory chips consist of vast arrays of storage cells which can be addressed by wordlines and bitlines. Each cell corresponds to one bit. The most commonly used cell design used in current dynamic random access memories(DRAMs) comprise a transfer gate(usually an MOS field-effect-transistor (MOSFET) and a storage node consisting of a capacitor. DRAM cells are, by necessity of high density and of simple design. To this end, the MOSFET-capacitor combination serves quite well. Static-random-access-memories (SRAMs) are slightly more complex, requiring four to six MOSFETs per cell.
The cell quantity requirements for memory are increasing at a phenomenal rate. Whereas the SRAMs of 1991 were of the order of 4 megabits, the density by the year 2001 is predicted to be 256 megabits or more. DRAMs have even greater cell density requirements. See eg. S. Wolf, "Silicon Processing for the VLSI Era", Vol.II, Lattice Press, Sunset Beach, Calif. (1990) p.598ff, and Vol.III(1995) p.275. The occurrence of a single defect in such a complex integrated circuit(IC) renders the entire body useless.
Obviously, the manufacturing functional yield of memory chips would rapidly approach zero if steps were not taken to circumvent such defective components. To this end, additional segments of memory circuits are provided on the IC chip as replacements for defective segments. Fortunately, memory arrays, by virtue of their repetitive design, lend themselves particularly well to the incorporation of such redundant segments. Although, additional space is required for these extra circuits, the yield benefits they provide make them very cost effective.
The manner in which these redundant segments are utilized and defective segments deleted is accomplished by means of laser trimming(LT). A description of the design layout and implementation of such redundant circuits need not be given here but may be found in Motonami et.al., U.S. Pat. No. 5,241,212. The segments are provided with fusible links or fuses which are blown as required, by a laser, after IC processing has been completed and functional testing with probes is possible. The functional testing determines which segments are defective and a laser, usually a neodymium YAG laser, is directed at the appropriate fusible links, thereby breaking the circuit.
The fusible links are formed as part of one of the metallization layers of the IC. Typically, a lower level, such as a polysilicon level is used. This level would, for example, contain the word-lines of a DRAM array. Prior to LT, the interlevel dielectric layers above the fusible link are sometimes removed entirely and replaced by a thinner protective layer to provide a short uniform path for the laser and confine the resultant debris. In other cases, the thick dielectric layers are etched down to a pre-determined thickness above the link. The laser energy required to blow the fuse is proportional to the thickness of the dielectric material above the fuse.
The laser spot is typically about 5.times.5 microns in size and its target opening at the fusible link is of the order of less than 10 microns. The positioning of the laser is determined by referencing one or two "L" shaped alignment marks located on a top layer of the die. These alignment marks are precisely located with respect to the lower level fusible links by conventional photolithographic alignment techniques familiar to those skilled in the art. Caldwell, U.S. Pat No. 5,401,691 discusses such techniques for the accurate propagation of alignment marks through the various processing levels including those involving chemical-mechanical-polishing(CMP) planarization. Another variation for assuring propagation of alignment marks during processing of ICs is given by Barber and Mayernik, U.S. Pat No. 5,314,837.
Kostelak, U.S. Pat. No. 4,992,394 provides means for enhancing the contrast of alignment marks for use with electron-beam lithography.
The alignment mark itself, is "L" shaped; the perpendicular legs of the "L" coinciding with the x and y axes of the IC arrays. In a prior art configuration shown in FIG. 1, the mark 36 is formed from the metal layer 18, typically an Al/Cu/Si Alloy. The mark is patterned in a square or rectangular site 30 located in the saw-kerf region of the wafer.
A cross section of the mark 36 at the region designated by X1--X1 in FIG. 1, is shown in FIG. 2. Layered upon the silicon wafer 10 under the mark, are the interlevel-dielectric layers(ILD1) 12 and (ILD2) 14. In the IC regions, ILD1 12 separates a first and a second polysilicon level. A first metallization level resides over ILD2 14 and a second metallization layer 18 is atop the inter-metal-dielectric layer(IMD) 16. By process design, these same dielectric layers also reside over the multiple fusible links which participate in the redundancy arrangements. For the purpose of this discussion an IC design using two polysilicon and two metallization levels is used for illustration. For ICs having more than two levels, the discussion deals with the uppermost two metallization levels. Thus the alignment marks are formed within the last interconnection level.
In order to provide a mark with a sharp edge profile, an anti-reflective-coating(ARC) 20 has been applied over the metal layer in which the mark is formed. This typically consists of a layer of titanium nitride(TiN) between about 200 to 800 Angstroms thick. This material is deposited over the metal layer 18 prior to the metal lithography to prevent radiation from the photoresist exposure from reflecting off the metal and exposing resist outside of the designated pattern. The photoresist mask is next applied, patterned and the ARC and metal layers are etched by reactive-ion-etching(RIE) using BCl.sub.3 for the TiN and Cl.sub.2 for the Al alloy to form the "L" shaped alignment marks.
Referring now to FIG. 3, there are shown together, a cross section of the wafer in the region of a polysilicon fuse 40 and a corresponding cross section in the area of the alignment mark 36. The fuse 40, in this example, is a portion of a word-line which lies over a region of field isolation 42. The wafer has been processed to a point where a second metallization layer 18 and an ARC layer 20 have been patterned over the IMD layer 16. The alignment mark 36 is formed from the ARC layer 20 and the metallization layer 18.
A passivation layer 22 of between about 2,000 to 10,000 Angstroms of silicon oxide or silicon nitride is deposited over the wafer. Photoresist 24 is applied to define the window outline 30 of the alignment mark as well as the access opening to the fuse 34.
Referring now to FIG. 4, Reactive-ion-etching using tetrafluoromethane(CF.sub.4) alone or in combination with trifluoromethane(CHF.sub.3), in an argon carrier gas, is used to etch the fuse openings through the passivation layer 22 and the various ILDs(12-16) to within about 3,000 to 5,000 Angstroms over the subjacent polysilicon fuse 40. The residual dielectric material serves to contain the debris from the blown fuse. During this etch the regions 32 of the alignment site 30 are also deeply recessed as shown in FIG. 4. The deep recessions harbor residues and other debris which are difficult to remove. These residues result primarily, from the processing of an additional passivation layer of polyimide which is applied and patterned with photoresist after the deep recessions are formed. Such final processing must be completed before the wafer can be tested in order to determine where the laser trimming is to be applied.
Topographic irregularities caused by the residues interfere with the functionality of the alignment mark as is illustrated in FIG. 5. In this figure there is shown the effect of a defect or particle 50 in the region adjacent to the alignment mark on the laser scanning signal which seeks the edges of the alignment mark for calibration of the LT tool. The alignment laser travels along the path indicated by the line Y1-Y2 shown in FIG. 5A. The defect 50 is located in this path. The corresponding scan, shown in FIG. 5B contains an unwanted peak PX caused by the defect. Peaks P1 and P2 are produced by the edges E1 and E2 of the alignment mark 18. The apparatus aligns itself to a central point CP between the peaks P1 and P2.
The presence multiple defects in the region of the alignment scan can cause extraneous "noise" in the laser scan resulting in serious alignment errors.
Kawai, U.S. Pat No. 5,369,050 provides a method for forming a raised alignment mark having a groove around it. The groove provides the necessary step for sensing the mark. Tsuji and Haraguchi, U.S. Pat No. 5,157,003 discuss the formation of an alignment mark having greater depth than surrounding device areas etched in the same process step. They accomplished this by using two masking steps on the same photoresist pattern.
In each of the two preceding cases the prior art process did not provide for a sufficient alignment mark step to be adequately detected. In the present case, the prior art process provides far too great a step.